Intel rushes to exascale with redesigned supercomputing chip
20 November 2013 | 0
In the rush to exascale computing, Intel is making a small change that could have a big impact on system design with its upcoming Xeon Phi chip.
Intel has promised big performance and power improvements with the redesigned chip, code-named Knights Landing, which analysts said could ship next year or 2015. The chip will also have interconnect and memory advances, Intel has said, that could separate it from other co-processors like graphics processors, which are widely used to accelerate technical computing.
Knights Landing will have many cores and could function as a primary CPU in a supercomputer, or also as a co-processor that slides into a PCI-Express slot. This is a significant change from the current Xeon Phi chip, code-named Knights Corner, which is available only as a co-processor and requires a server CPU like a Xeon E5 to host applications and run an OS.
“The chip itself is no longer a co-processor. It runs the OS and all of the computation on the same chip,” said Nathan Brookwood, principal analyst at Insight 64.
Supercomputers today harness the joint computing power of CPUs and co-processors like the Phi or Nvidia’s Tesla GPUs to process applications in areas such as medicine, defence, energy and science. But with Knights Landing functioning both as a primary CPU and accelerator, there is less need for extra components, which could reduce the size and cost of building a supercomputer.
“It dramatically increases performance because you don’t have to move the data back and forth into memory and accelerator boards,” Brookwood said, adding that fewer components means a lower energy bill.
The US, China and Japan are in a race to reach the milestone of exascale computing. But design constraints and high power consumption have limited the development of such supercomputers, and companies including Cray, IBM, Intel and Nvidia are developing new servers and power-efficient mega chips that can deliver massive amounts of performance.
The fastest supercomputer in the world, China’s Tianhe-2, delivers peak performance of 33.86 petaflops. The supercomputer has Intel’s Xeon E5 chips as primary CPUs, and current Xeon Phi co-processors. Chip companies have set a goal of 2020 for the first exaflop supercomputer, which will deliver performance of about 1,000 petaflops.
The Knights Landing chip will have architectural improvements, faster throughput and easier memory access, said Raj Hazra, vice president and general manager of technical computing at Intel.
Hazra did not provide specifics on hardware improvements in the chip. But single-threaded and parallel applications can be processed through Knights Landing, Hazra said.
“We cater to all those constraints and needs in this one single product,” Hazra said.
As supercomputing speeds increase, the integration of a CPU and accelerator will provide highly parallel applications with more internal bandwidth, said Patrick Moorhead, president and principal analyst at Moor Insights and Strategy.
“With Knights Landing as a host CPU, Intel hopes to serve those massively parallel workloads that need minimal latency that comes with today’s accelerators that use the PCI-Express bus,” Moorhead said.
Real World Tech analyst David Kanter said the chip could have many embedded DRAM units, as in the company’s recent chips code-named Haswell. Additionally, lots of larger-capacity DRAM could dot the chip, much like memory on graphics cards.
Many companies are heading in the direction of stacking chips — also called 3D structuring — on top of each other to save space and improve throughput. But the memory units in Knights Landing may not be stacked as it could be expensive and cause more leakage, Kanter said.
“Stacking memory on top makes sense, but if you have a 200- to 300-watt chip under it, doesn’t make sense,” Kanter said.
A major improvement on Knights Landing is support for single-threaded applications, Kanter said. Accelerator chips today focus mostly on highly parallel applications, leaving single threaded applications hanging to be processed by other hardware units. Such computing can be inefficient, Kanter said.
Also, developers will not have to worry about writing code in which processing is redirected to different hardware, analysts said.
Knights Landing will be made using the 14-nanometer manufacturing process. The first 14nm chips are expected to reach PCs in the second half of this year, and Knights Landing could follow.