IBM Research achieves record data speeds
14 February 2014 | 0
IBM Research has successfully tested a new prototype network chip that can transmit data at rates between 200 and 400 Gigabits per second.
To put that in context, that would mean 40,000 songs downloaded, or an ultra-high definite, 4K movie in seconds. The device was presented at the International Solid-State Circuits Conference (ISSCC) in San Francisco.
Scientists at IBM Research and Ecole Polytechnique Fédérale de Lausanne (EPFL) have been developed this ultra-fast and energy efficient analogue-to-digital converter (ADC) technology to enable complex digital equalisation across long-distance fibre channels.
An ADC converts analogue signals to digital, approximating the right combination of zeroes and ones to digitally represent the data so it can be stored on computers and analysed for patterns and predictive outcomes.
For example, scientists will use hundreds of thousands of ADCs to convert the analogue radio signals that originate from the Big Bang 13 billion years ago to digital. It is part of a collaboration called Dome between ASTRON, the Netherlands Institute for Radio Astronomy, DOME-South Africa and IBM to develop a fundamental IT roadmap for the Square Kilometer Array (SKA), an international project to build the world’s largest and most sensitive radio telescope.
The radio data that the SKA collects from deep space is expected to produce 10 times the global internet traffic and the prototype ADC would be an ideal candidate to transport the signals fast and at very low power — a critical requirement considering the thousands of antennas which will be spread over 3,000 kilometres.
“Our ADC supports IEEE standards for data communication and brings together speed and energy efficiency at 32 nanometres enabling us to start tackling the largest Big Data applications,” said Dr Martin Schmatz, systems department manager at IBM Research. “With Semtech as our partner, we are bringing our previous generation of the ADC to market less than 12 months since it was first developed and tested.”
Semtech signed a non-exclusive technology licensing agreement, including access to patented designs and technological knowledge, with IBM to develop the technology for its own family of products ranging from optical and wireline communications to advanced radar systems.
“Through leveraging the IBM 32nm SOI process with its unique feature set, we are developing products that are well-suited for meeting the challenge presented by the next step in high performance communications systems such as 400 Gb/s Optical systems and Advanced Radar systems. We are also seeing an expanding range of applications in the existing radio frequency communications marketplace where high-speed digital logic is replacing functions that have been traditionally performed by less flexible analogue circuitry,” said Craig Hornbuckle, chief systems architect, Semtech.
The 64 GS/s (giga-samples per second) chips for Semtech will be manufactured at IBM’s 300mm fab in East Fishkill, New York in a 32 nanometer silicon-on-insulator CMOS process and has an area of 5 mm2. This core includes a wide tuning millimeter wave synthesiser enabling the core to tune from 42 to 68 GS/s per channel with a nominal jitter value of 45 femtoseconds root mean square. The full dual-channel 2×64 GS/s ADC core generates 128 billion analogue-to-digital conversions per second, with a total power consumption of 2.1 Watts.
The technological details of the latest ADC have been published in a paper with the EPFL and was presented yesterday at the International Solid-State Circuits Conference (ISSCC).