Researchers at the Science Foundation Ireland-funded materials science centre Amber and the School of Chemistry at Trinity College Dublin have developed a solution to increase the speed interaction between processor and memory in electronic devices such as computers and smartphones.
Instead of each memory cell storing just a single piece of information, the team developed a multilevel memory in which it is possible to programme a number of stored bits into a single cell. Multilevel memory increases communication speed by reducing the number of memory cells.
Team leader Prof John J. Boland explained: “Processors and memory communicate using the clunky language of binary code. Conventional on-chip memory stores information as ones and zeroes, which reflects the presence or absence of charge at the memory location. For example, 2014 in binary language requires 11 cells of memory. It takes time for the computer to access such a large number of cells and so the overall performance is impaired. The new process reduces the number of cells required.”
The scheme proposed by the researchers operates on a different principle. The resistance to charge flow – called resistive memory – leads to more streamlined processing with fewer cells but with each having multiple memory levels. A particular advantage of the new approach is that it is possible to arbitrarily tune the number of memory levels within each cell.
“The discovery opens up a host of possibilities for the consumer leading to smaller, cheaper and faster electronics. Having demonstrated six memory levels per cell, we believe the technology can be developed to display even more memory levels per cell,” Prof Boland said. “A memory language with greater density can increase the efficiency and speed of desktop and mobile technology by reducing the number of memory locations.
“Further research will be focused on integrating this technology with existing industry fabrication capabilities, so that society can continue to reap the benefits with new and improved technology.”
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